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CS8140, CS8141 5.0 V, 500 mA Linear Regulator with ENABLE, RESET, and Watchdog
The CS8140 and CS8141 are linear regulators suited for microprocessor applications in automotive environments. These ON Semiconductor parts provide the power for the microprocessors along with many of the control functions needed in today's computer based systems. Incorporating all of these features saves both cost, and board space. Packages are available for surface mounting as well as through hole mounting. The CS8141 has the same feature set as the CS8140 with the exception of the response to the watchdog signals (WDI). The CS8141 only responds to input signals (WDI) which are below the preset watchdog frequency threshold. Features * 5.0 V 4.0%, 500 mA Output Voltage * P Compatible Control Functions - Watchdog - RESET - ENABLE * Low Dropout Voltage (1.25 V @ 500 mA) * Low Quiescent Current (7.0 mA @ 500 mA) * Low Noise, Low Drift * Low Current SLEEP Mode (IQ = 250 A) * Fault Protection - Thermal Shutdown - Short Circuit - 60 V Peak Transient Voltage
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TO-220 SEVEN LEAD T SUFFIX CASE 821E 7 1 TO-220 SEVEN LEAD TVA SUFFIX CASE 821J TO-220 SEVEN LEAD THA SUFFIX CASE 821H 1 7 D2PAK 7-PIN DPS SUFFIX CASE 936H 7
1
1
24 1
SO-24L DW SUFFIX CASE 751E
DIP-14 N SUFFIX CASE 646 14 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 14 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2001
1
September, 2001 - Rev. 13
Publication Order Number: CS8140/D
CS8140, CS8141
PIN CONNECTIONS
TO-220 SEVEN LEAD NC Delay WDI VOUT Sense NC NC NC NC NC NC GND SO-24L 1 24 RESET ENABLE NC VIN GND NC NC NC NC NC NC NC 1 Delay WDI VOUT Sense NC NC NC DIP-14 14 RESET ENABLE VIN GND NC NC GND
1
D2PAK SEVEN PIN
Tab = GND Pin 1. VIN 2. ENABLE 3. RESET 4. GND 5. Delay 6. WDI 7. VOUT
1
VIN Overvoltage Overtemperature
Reference & Bias
Regulation ENABLE WDI Control Logic ENABLE RESET Delay
VOUT Short Circuit Internally tied on TO-220 & D2PAK Sense RESET
Undervoltage GND Watchdog
Delay
Figure 1. Block Diagram
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CS8140, CS8141
MAXIMUM RATINGS*
Rating Input Operating Range Peak Transient Voltage (46 V Load Dump @ 14 V VBAT) Electrostatic Discharge (Human Body Model) WDI Input Signal Range Internal Power Dissipation Junction Temperature Range (TJ) Storage Temperature Range ENABLE Package Thermal Resistance, TO-220 Seven Lead Junction-to-Case, RJC Junction-to-Ambient, RJA Package Thermal Resistance, D2PAK 7-Pin Junction-to-Case, RJC Junction-to-Ambient, RJA Package Thermal Resistance, SO-24L Junction-to-Case, RJC Junction-to-Ambient, RJA Package Thermal Resistance, DIP-14 Junction-to-Case, RJC Junction-to-Ambient, RJA Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value -0.5 to 26 60 4.0 -0.3 to 7.0 Internally Limited -40 to +150 -65 to +150 -0.3 to VIN 1.6 50 1.5 10-50 16 80 48 85 260 peak 230 peak Unit V V kV V - C C V C/W C/W C/W C/W C/W C/W C/W C/W C
*The maximum package power dissipation must be observed. Depending on thermal properties of substrate RJA = RJC + RCA. 1. 10 second maximum. 2. 60 seconds max above 183C.
ELECTRICAL CHARACTERISTICS (7.0 VIN 26 V, 5.0 mA IOUT 500 mA, -40C TJ 150C, -40C TA 125C, unless otherwise noted.) Note 3.
Characteristic Output Stage (VOUT) Output Voltage, VOUT Dropout Voltage (VIN - VOUT) Line Regulation Load Regulation Output Impedance, ROUT Quiescent Current, (IQ) Active Mode Sleep Mode Ripple Rejection Current Limit Thermal Shutdown Overvoltage Shutdown VOUT < 1.0 V 7.0 V VIN 26 V, 5.0 mA < IOUT < 500 mA IOUT = 500 mA IOUT = 50 mA, 7.0 V VIN 26 V, VIN = 14 V, 50 mA IOUT 500 mA 500 mA DC and 10 mA AC, 100 Hz f 10 kHz 0 IOUT 500 mA, 7.0 V VIN 26 V IOUT = 0 mA, VIN = 13 V, ENABLE = 0 V 7.0 V VIN 17 V, IOUT = 250 mA, f = 120 Hz - - 4.8 - - - - 5.0 1.25 5.0 5.0 200 5.2 1.50 25 80 - V V mV mV m Test Conditions Min Typ Max Unit
- - 60 700 150 30
7.0 0.25 75 1200 180 34
15 0.50 - 2000 - 38
mA mA dB mA C V
3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
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CS8140, CS8141
ELECTRICAL CHARACTERISTICS (continued) (7.0 VIN 26 V, 5.0 mA IOUT 500 mA, -40C TJ 150C,
-40C TA 125C, unless otherwise noted.) Note 4. Characteristic ENABLE Threshold HIGH LOW Threshold Hysteresis RESET Threshold HIGH VR(HI) Threshold LOW VR(LOW) Threshold Hysteresis (VRH) RESET Output Leakage RESET = HIGH Output Voltage Low (VL(LOW)) Output Voltage Low (VRpeak) Delay Times tPOR Delay Times tWDI(RESET) Watchdog Input Voltage High Input Voltage Low Input Current Threshold Frequency fWDI(LOWER) Threshold Frequency fWDI(UPPER) (Note 6.) WDI VOUT CDELAY = 0.1 F CDELAY = 0.1 F - - 2.0 - - 64 218 - - 0 77 262 - 0.8 10 96 326 V V A Hz Hz VOUT Increasing VOUT Decreasing (HIGH - LOW) VOUT VR(HI) 1.0 V VOUT VR(LOW), RP = 2.7 k, Note 5. VOUT, Power up, Power down CDELAY = 0.1 F CDELAY = 0.1 F 4.65 4.50 150 - - - 30 0.5 4.90 4.70 200 - 0.1 0.6 47.5 1.0 VOUT - 0.05 4.90 250 25 0.4 1.0 65 1.5 V V mV A V V ms ms VOUT 0.5 V, (VOUT(ON)) VOUT < 0.5 V, (VOUT(OFF)) (HIGH - LOW) - 3.5 - 4.05 3.95 100 4.50 - - V V mV Test Conditions Min Typ Max Unit
4. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 5. RP is connected to RESET and VOUT. 6. CS8140 only.
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD # TO-220 1 2 3 D2PAK 1 2 3 SO-24L 21 23 24 DIP-14 12 13 14 LEAD SYMBOL LEAD SYMBOL VIN ENABLE RESET FUNCTION Supply voltage to IC, usually direct from the battery. CMOS compatible logical input. VOUT is disabled when ENABLE is LOW and WDI is beyond its preset limits. CMOS compatible output lead. RESET goes low whenever VOUT drops below 4.5% of it's typical value for more than 2.0 s or WDI signal falls outside it's window limits. Ground Connection. Timing capacitor for Watchdog and RESET functions. CMOS compatible input lead. The Watchdog function monitors the falling edge of the incoming digital pulse train. The signal is usually generated by the system microprocessor. Regulated output voltage, 5.0 V (typ). No connection. Kelvin connection which allows remote sensing of output voltage for improved regulation.
4 5 6
4 5 6
12, 20 2 3
8, 11 1 2
GND Delay WDI
7 - -
7 - -
4 1, 6-11, 13-19, 22 5
3 5-7, 9, 10 4
VOUT NC Sense
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TYPICAL PERFORMANCE CHARACTERISTICS
5.5 5.0 4.5 4.0 VOUT (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
0 1 2 3 4 5 6 7 8 9 10 RLOAD 10 VENABLE = VIN RLOAD = NO LOAD RLOAD = 6.67
5.5 5.0 4.5 4.0 VOUT (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
0
VENABLE = VIN TEMP = 125C TEMP = -40C TEMP = 25C
1
2
3
4
5
6
7
8
9
10
VIN (V)
VIN (V)
Figure 2. VOUT vs. VIN over RLOAD; T = 25C
Figure 3. VOUT vs. VIN Over Temperature; RLOAD = 25
1800 1600 Dropout Voltage (mV) Load Regulation (mV) 1400 1200 1000 800 600 400 200 0
0 100 200 300 400 500 600 700 800 25C -40C 125C
3.5 0 -3.5 -7 -10.5 -14 -17.5 -21 -24.5 -28 -31.5 -35
0 100 200 300 400 125C 25C
-40C
VIN = 14 V
500
600
700
800
IOUT (mA)
IOUT (mV)
Figure 4. Dropout Voltage vs. Output Current Over Temperature
18 16 Line Regulation (mV) 14 12 10 8 6 4 2 0 -2 -4 -6
0 100 200 300 125C 400 500 600 700 800 25C -40C
Figure 5. Load Regulation vs. Output Current Over Temperature
10 9 8 IQ (mA) 7 6 5 4
0 100 200 300 400 500 600 700 800 125C 25C
VIN = 14 V
VIN = 14 V -40C
IOUT (mA)
IOUT (mA)
Figure 6. Line Regulation vs. Output Current Over Temperature http://onsemi.com
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Figure 7. Quiescent Current vs. Output Current Over Temperature
CS8140, CS8141
TYPICAL PERFORMANCE CHARACTERISTICS
20 18 16 14 IQ (mA)
RLOAD = 6.67 RLOAD = 25 RLOAD = NO LOAD VENABLE = VIN
20 18 16 14 IQ (mA) 12 10 8 6
TEMP = 125C TEMP = -40C VENABLE = VIN
TEMP = 25C
12 10 8 6 4 2 0
0 1 2 3 4 5 6
4 2
7 8 9 10
0
0
1
2
3
4
5
6
7
8
9
10
VIN (V)
VIN (V)
Figure 8. Quiescent Current vs. VIN Over RLOAD; T = 25C
Figure 9. Quiescent Current vs. VIN Over Temperature; RLOAD = 25
300 280 260 240
107
Upper Threshold
106 WDI Threshold 105 104 103 102
Lower Threshold Lower Threshold Upper Threshold
Frequency (Hz)
220 200 180 160 140 120 100 80
CDELAY = 0.1 F
101 100
101 102 103 104 105 106
60 -40 -30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
10
TJ (C)
Capacitance (pF)
Figure 10. Watchdog Frequency Thresholds vs. Temperature
90 80 70 Rejection (dB) 60 50 40 30 20 10 0
100 101 102 COUT = 10 F, ESR = 1.0 COUT = 10 F, ESR = 1.0 IO = 250 mA
Figure 11. Watchdog Frequency Threshold vs. CDELAY
2000 RESET Output Voltage (mV)
CO = 10 F, ESR = 1.0 & 0.1 F, ESR = 0
1800 1600 1400 1200 1000 800 600 400 200
VIN = 5.0 V
103
104
105
106
107
108
0
1
5
10
15
20
25
30
35
40
Frequency (Hz)
RESET Output Current (mA)
Figure 12. Ripple Rejection vs. Frequency
Figure 13. RESET Output Voltage vs. Output Current
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DEFINITION OF TERMS Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Current Limit: Peak current that can be delivered to the output.
CIRCUIT DESCRIPTION The CS8140 is a 5.0 V Watchdog Regulator with protection circuitry and three logic control functions that allow a microprocessor to control its own power supply. The CS8140 is designed for use in automotive, switch mode power supply post regulator, and battery powered systems. Basic regulator performance characteristics include a low noise, low drift, 5.0 V 4.0% precision output voltage with low dropout voltage (1.25 V @ IOUT = 500 mA) and low quiescent current (7.0 mA @ IOUT = 500 mA). On board short circuit, thermal, and overvoltage protection make it possible to use this regulator in particularly harsh operating environments. The Watchdog logic function monitors an input signal (WDI) from the microprocessor or other signal source. When the signal frequency moves outside externally programmable window limits, a RESET signal is generated (RESET). An external capacitor (CDELAY) programs the watchdog window frequency limits as well as the power on reset (POR) and RESET delay. The RESET function is activated by any of three conditions: the watchdog signal moves outside of its preset limits; the output voltage drops out of regulation by more than 4.5%; or the IC is in its power up sequence. The RESET signal is independent of VIN and reliable down to VOUT = 1.0 V. In conjunction with the Watchdog, the ENABLE function controls the regulator's power consumption. The CS8140's output stage and its attendant circuitry are enabled by setting the ENABLE lead high. The regulator goes into sleep mode when the ENABLE lead goes low and the watchdog signal moves outside its preset window limits. This unique combination of control functions in the CS8140 gives the microprocessor control over its own power down sequence: i.e. it gives the microprocessor the flexibility to perform housekeeping functions before it powers down. The CS8141 has the same features as the CS8140, except that the CS8141 only responds to input signals (WDI) which are below the preset watchdog frequency threshold.
VOLTAGE REFERENCE AND OUTPUT CIRCUITRY Precision Voltage Reference
The regulated output voltage depends on the precision band gap voltage reference in the IC. By adding an error amplifier into the feedback loop, the output voltage is maintained within 4.0% over temperature and supply variation.
Output Stage
The composite PNP-NPN output structure (Figure 14) provides 500 mA (min) of output current while maintaining a low drop out voltage (1.25 V) and drawing little quiescent current (7.0 mA).
VIN
VOUT
Figure 14. Composite Output Stage of the CS8140/1
The NPN pass device prevents deep saturation of the output stage which in turn improves the IC's efficiency by preventing excess current from being used and dissipated by the IC.
Output Stage Protection
The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 15). If the input voltage rises above 30 V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Using an emitter sense scheme, the amount of current through the NPN pass transistor is monitored. Feedback
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CS8140, CS8141
circuitry insures that the output current never exceeds a preset limit.
> 30 V VIN VOUT (b) IO
The lower and upper window threshold limits of the watchdog function are set by the value of CDELAY. The limits are determined according to the following equations for the CS8140:
(a)
tWDI(LOWER) + (1.3 fWDI(LOWER) + (7.69 tWDI(UPPER) + (3.82 fWDI(UPPER) + (2.62
105)CDELAY or 10-6)CDELAY-1 10-4)CDELAY or 10-5)CDELAY-1
Load Dump
Short Circuit
Thermal Shutdown
Figure 15. Typical Circuit Waveforms for Output Stage Protection
For the CS8141 the lower limit is determined by the equations in (a) above. The capacitor CDELAY also determines the frequency of the RESET signal and the POWER-ON-RESET (POR) delay period.
RESET Function
Should the junction temperature of the power device exceed 180C (typ), the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.
REGULATOR CONTROL FUNCTIONS
The CS8140 differs from all other linear regulators in its unique combination of control features.
Watchdog and ENABLE Function
VOUT is controlled by the logic functions ENABLE and Watchdog (Table 1).
Table 1. VOUT as a Function of ENABLE and Watchdog
VOUT (V) WDI ENABLE H L Slow 5 0 Normal 5 5 Fast 5 0 High 5 0 Low 5 0
The RESET function is activated when the Watchdog signal is outside of its preset window (Figure 16), when the regulator is in its power up state (Figure 17) or when VOUT drops below VOUT -4.5% for more than 2.0 s (Figure 18) If the Watchdog signal falls outside of the preset voltage and frequency window, a frequency programmable pulse train is generated at the RESET lead (Figure 16) until the correct Watchdog input signal reappears at the lead. The duration of the RESET pulse is determined by CDELAY according to the following equation:
tWDI(RESET) + (1.0 104)CDELAY
RESET CIRCUIT WAVEFORMS WITH DELAYS INDICATED
As long as ENABLE is high or ENABLE is low and the Watchdog signal is normal, VOUT will be at 5.0 V (typ). If ENABLE is low and the Watchdog signal moves outside programmable limits, the output transistor turns off and the IC goes into SLEEP mode. Only the ENABLE circuitry in the IC remains powered up, drawing a quiescent current of 250 A. The Watchdog monitors the frequency of an incoming WDI signal. If the signal falls outside of the WDI window, a frequency programmable pulse train is generated at the RESET lead (Figure 16) until the correct Watchdog input signal reappears at the lead (ENABLE = HIGH).
If an undervoltage condition exists, the voltage on the RESET lead goes low and the delay capacitor, CDELAY, is discharged. RESET remains low until output is in regulation, the voltage on CDELAY exceeds the upper switching threshold and the Watchdog input signal is within its set window limits (Figures 17 and 18). The delay after the output is in regulation is:
tPOR(typ) + (4.75 105)CDELAY
The RESET delay circuit is also programmed with the external cap CDELAY. The output of the reset circuit is an open collector NPN. RESET is operational down to VOUT = 1.0 V. Both RESET and its delay are governed by comparators with hysteresis to avoid undesirable oscillations.
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CS8140, CS8141
Batt
VIN
Batt
VOUT When Watchdog is Held High and ENABLE = HIGH
ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI held High
Batt
VIN
Batt
VOUT When Watchdog is Held Low and ENABLE = HIGH
ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI held Low
Batt
VIN
Batt
VOUT When Watchdog is too Slow and ENABLE = HIGH
ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation Slow WDI signal
Batt
VIN
Batt
VOUT When Watchdog is too Fast and ENABLE = HIGH
ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation
Batt
Fast WDI signal
VIN
Batt
WDI Held High After a Normal Period of Operation; ENABLE = LOW
ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI Sleep Mode high POR Normal Operation
Batt
VIN
Batt
WDI Held Low or is too Slow after a Normal Period of Operation; ENABLE = LOW
ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI low Sleep Mode POR Normal Operation
Batt
WDI Frequency Rises Above the Upper Frequency Threshold After a Normal Period of Operation; ENABLE = LOW (for CS8140 only)
VIN ENABLE WDI 0 V RESET 0 V VOUT 0 V
Batt
POR
Normal Operation
Sleep Mode
POR
Normal Operation
Figure 16. Timing Diagrams for Watchdog and ENABLE Functions http://onsemi.com
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CS8140, CS8141
VOUT VR(HI) VOUT VOUT -4.5%
< 2.0 s 2.0 s
VR(LO)
RESET VR(LO) VR(PEAK) RESET 5.0 V
tPOR
tPOR
Figure 17. Power RESET and Power Down
Figure 18. Undervoltage Triggered RESET
APPLICATION NOTES
CS8140 DESIGN EXAMPLE
The CS8140 with its unique integration of linear regulator and control features: RESET, ENABLE and WATCHDOG, provides a single IC solution for a microprocessor power supply. The reset delay, reset duration and watchdog frequency limits are all determined by a single capacitor. For a particular microprocessor the overriding requirement is usually the reset delay (also known as power on reset). The capacitor is chosen to meet this requirement and the reset duration and watchdog frequency follow. The reset delay is given by:
tPOR(typ) + (4.75 105)CDELAY
tWDI(LOWER) + (1.3 tWDI(UPPER) + (3.82
105)CDELAY 104)CDELAY
There is a tolerance of 20% due to the CS8140. With a capacitor tolerance of 10%:
tWDI(LOWER) + (1.3 tWDI(UPPER) + (3.82 105) 104) 1.2 0.8 1.1 0.9 CDelay CDelay
tWDI(LOWER) + 141 ms (max) tWDI(UPPER) + 22.5 ms (max) tWDI(LOWER) + (1.3 tWDI(UPPER) + (3.82 105) 104) 0.8 1.2 0.9 1.1 CDELAY CDELAY
Assume that the reset delay must be 200 ms minimum. From the CS8140 data sheet the reset delay has a 37% tolerance due to the regulator. Assume the capacitor tolerance is 10%.
tPOR(min) + (4.75 105 0.63) CDELAY 0.9
tWDI(LOWER) + 76 ms (min) tWDI(UPPER) + 41 ms (min)
t (min) CDELAY(min) + POR 2.69 105 CDELAY(min) + 0.743 mF
The software must be written so that a watchdog signal arrives at least every 76 ms but not faster than every 41 ms (Figure 19).
FAIL PASS FAIL
Closest standard value is 0.82 F. Minimum and maximum delays using 0.82 F are 220 ms and 586 ms. The duration of the reset pulse is given by:
TWDI(RESET)(typ) + (1.0 104) CDELAY
This has a tolerance of 50% due to the IC, and 10% due to the capacitor. The duration of the reset pulse ranges from 3.69 ms to 13.5 ms. The watchdog signal can be expressed as a frequency or time. From a programmers point of view, time is more useful since they must ensure that a watchdog signal is issued consistently several times per second. The maximum and minimum watchdog times are given by:
Hz ms
7 141
9 107
13 76
24 41
32 31
44 22.5
C = 0.1 F 10%
Figure 19. WDI Signal for CDelay = 0.82 F using CS8140
The CS8141 is identical to the CS8140 except that the CS8141 only has a lower watchdog frequency threshold. The designer using this part need only be concerned with tWDI(LOWER) as shown in Figure 20.
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CS8140, CS8141
When the voltage across C1 reaches 3.95 V ( the enable threshold), the output switches on and VOUT rises to 5.0 V. After a delay period determined by CDelay, a frequency programmable reset pulse train is generated at the reset output. The pulse train continues until the correct watchdog signal appears at the WDI lead. C1 is now left to discharge through the input impedance of the enable lead (approximately 150 k) and the enable signal disappears. The output voltage remains at 5.0 V as long as the CS8140 continues to receive the correct watchdog signal. The microprocessor can power itself down by terminating its watchdog signal. When the microprocessor finishes its housekeeping or power down software routine, it stops sending a watchdog signal. In response, the regulator generates a reset signal and goes into a sleep mode where VOUT drops to 0 V, shutting down the microprocessor.
FAIL PASS
Hz ms
7 141
13 76
Figure 20. WDI Signal for CDelay = 0.82 F using CS8141 ENERGY CONSERVATION AND SMART FEATURES
Energy conservation is another benefit of using a regulator with integrated microprocessor control features. Using the CS8140 or CS8141 as indicated in Figure 21, the microprocessor can control its own power down sequence. The momentary contact switch quickly charges C1 through R1.
9.0 V
VIN Switch R1 110 K ENABLE C1 0.1 F CDELAY C2 0.1 F
VOUT
CS8140/1
RESET WDI
GND
VCC 10 F 2.7 k
Microprocessor
RESET WATCHDOG PORT
Figure 21. Application Diagram for CS8140. The CS8140 Provides a 5.0 V Tightly Regulated Supply and Control Function to the Microprocessor. In this Application, the Microprocessor Controls its own Power Down Sequence (see text).
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CS8140, CS8141
Battery C1 * 0.1 F (optional) Ignition VIN VOUT
CS8140
ENABLE DELAY RESET WDI GND
C2 * 10 F* 2.7 k RESET
VCC
0.1 F
WATCHDOG PORT R***
Microprocessor
*C1 is required if regulator is located far from the power source filter. **C2 is required for stability. ***R 80 k.
Figure 22. Application Diagram
STABILITY CONSIDERATIONS
The output or compensation capacitor C2 in Figure 22 helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in Figure 22 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Increase the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.
CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output regulator (Figure 23) is:
PD(max) + VIN(max) * VOUT(min) IOUT(max) ) VIN(max)IQ
(1)
where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max).
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IIN VIN
SMART REGULATOR(R)
Control Features IQ
IOUT VOUT
In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
HEAT SINKS
Figure 23. Single Output Regulator With Key Performance Parameters Labeled
A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA.
RQJA + RQJC ) RQCS ) RQSA
Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated:
RQJA + 150C * TA PD
(2)
(3)
The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA's less than the calculated value in equation 2 will keep the die temperature below 150C.
where: RJC = the junction-to-case thermal resistance, RCS = the case-to-heatsink thermal resistance, and RSA = the heatsink-to-ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it too is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
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CS8140, CS8141
MARKING DIAGRAMS
D2PAK SEVEN PIN 24 CS814x AWLYWW
CS814x AWLYWW
TO-220 SEVEN LEAD
SO-24L 14 CS814x AWLYYWW 1 1
DIP-14
CS814x AWLYYWW
1 1 x A WL, L YY, Y WW, W = 0 or 1 = Assembly Location = Wafer Lot = Year = Work Week
DEVICE ORDERING INFORMATION
Device CS8140YT7 CS8140YTVA7 CS8140YTHA7 CS8140YDPS7 CS8140YDPSR7 CS8140YDW24 CS8140YDWR24 CS8140YN14 CS8141YT7 CS8141YTVA7 CS8141YTHA7 CS8141YDPS7 CS8141YDPSR7 CS8141YDW24 CS8141YDWR24 CS8141YN14 Package TO-220 Seven Lead, Straight TO-220 Seven Lead, Vertical TO-220 Seven Lead, Horizontal D2PAK, 7-Pin D2PAK, 7-PIN SO-24L SO-24L DIP-14 TO-220 Seven Lead, Straight TO-220 Seven Lead, Vertical TO-220 Seven Lead, Horizontal D2PAK, D2PAK, 7-Pin 7-PIN Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 750 Tape & Reel 31 Units/Rail 1000 Tape & Reel 25 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 750 Tape & Reel 31 Units/Rail 1000 Tape & Reel 25 Units/Rail
SO-24L SO-24L DIP-14
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CS8140, CS8141
PACKAGE DIMENSIONS
TO-220 SEVEN LEAD T SUFFIX CASE 821E-04 ISSUE C
Q A G B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.003 (0.076) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. INCHES MIN MAX 0.600 0.610 0.386 0.403 0.170 0.180 0.028 0.037 0.045 0.055 0.088 0.102 0.018 0.026 1.028 1.042 0.355 0.365 5 _ NOM 0.142 0.148 0.490 0.501 0.045 0.055 MILLIMETERS MIN MAX 15.24 15.49 9.80 10.23 4.32 4.56 0.71 0.94 1.15 1.39 2.24 2.59 0.46 0.66 26.11 26.47 9.02 9.27 5 _ NOM 3.61 3.75 12.45 12.72 1.15 1.39
L U K
OPTIONAL CHAMFER
D
M M
SEATING PLANE
C V M J
H M
DIM A B C D G H J K L M Q U V
TO-220 SEVEN LEAD TVA SUFFIX CASE 821J-02 ISSUE A
-T- C -Q- B E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.540 0.555 0.050 BSC 0.570 0.595 0.014 0.022 0.785 0.800 0.322 0.337 0.073 0.088 0.090 0.115 0.146 0.156 0.289 0.304 0.164 0.179 0.460 0.475 3 MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 13.72 14.10 1.27 BSC 14.48 15.11 0.36 0.56 19.94 20.32 8.18 8.56 1.85 2.24 2.28 2.91 3.70 3.95 7.34 7.72 4.17 4.55 11.68 12.07 3
W U A HF L K M
D 0.356 (0.014)
M
7 PL
TQ
M
N S G J R
DIM A B C D E F G H J K L M N Q R S U W
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CS8140, CS8141
TO-220 SEVEN LEAD THA SUFFIX CASE 821H-02 ISSUE A
-T- C -Q- B E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. 1. LEADS MAINTAIN A RIGHT ANGLE WITH RESPECT TO THE PACKAGE BODY TO WITH $0.020". DIM A B C D E F G J K L M N Q S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.568 0.583 0.050 BSC 0.015 0.022 0.728 0.743 0.322 0.337 0.101 0.116 0.090 0.115 0.146 0.156 0.150 0.200 0.460 0.475 3 MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 14.43 14.81 1.27 BSC 0.38 0.56 18.49 18.87 8.18 8.56 2.57 2.95 2.28 2.91 3.70 3.95 3.81 5.08 11.68 12.07 3
W U A L F K
M
D 0.356 (0.014)
M
7 PL
J
M
TQ
G
N
S
D2PAK 7-PIN DPS SUFFIX CASE 936H-01 ISSUE O
-T- SEATING PLANE B 8 V A 1 2 34 5 6 7 K F G D
7 PL M DIM A B C D E F G H J K M N U V NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS B AND M. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAX. INCHES MIN MAX 0.326 0.336 0.396 0.406 0.170 0.180 0.026 0.036 0.045 0.055 0.058 0.078 0.050 BSC 0.100 0.110 0.018 0.025 0.204 0.214 0.055 0.066 0.000 0.004 0.256 REF 0.305 REF MILLIMETERS MIN MAX 8.28 8.53 10.05 10.31 4.31 4.57 0.66 0.91 1.14 1.40 1.41 1.98 1.27 BSC 2.54 2.79 0.46 0.64 5.18 5.44 1.40 1.68 0.00 0.10 6.50 REF 7.75 REF
M
C E
U
H J
0.13 (0.005)
TB
M
N
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CS8140, CS8141
SO-24L DW SUFFIX CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIP-14 N SUFFIX CASE 646-04 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.740 0.240 0.260 0.160 0.180 0.015 0.020 0.040 0.060 0.100 BSC 0.052 0.072 0.008 0.012 0.115 0.135 0.290 0.310 --10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 4.06 4.57 0.38 0.51 1.02 1.52 2.54 BSC 1.32 1.83 0.20 0.30 2.92 3.43 7.37 7.87 --10 _ 0.51 1.02
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
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CS8140, CS8141
Notes
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18
CS8140, CS8141
Notes
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19
CS8140, CS8141
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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CS8140/D

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